>Капитан ОЙчевидность ? 8)
>
>Не поленитесь заглянуть в nidia.c... Увы и ах - максимум NV_ARCH_40 &
>GF79xx. Дык, а руки на что
diff -u nvidia//nv_hw.c /tmp/nvidia//nv_hw.c
--- nvidia//nv_hw.c 2010-03-15 19:09:39.000000000 +0300
+++ /tmp/nvidia//nv_hw.c 2010-03-28 18:50:25.871159601 +0400
@@ -82,6 +82,8 @@
if (par->Architecture == NV_ARCH_40)
NV_WR32(par->PRAMDAC, 0x0300, NV_RD32(par->PRAMDAC, 0x0300));
+ if (par->Architecture == NV_ARCH_50)
+ NV_WR32(par->PRAMDAC, 0x0abc, NV_RD32(par->PRAMDAC, 0xabc));
return (cur & 0x01);
}
@@ -143,7 +145,32 @@
{
unsigned int pll, N, M, MB, NB, P;
- if (par->Architecture >= NV_ARCH_40) {
+ if (par->Architecture >= NV_ARCH_50) {
+ pll = NV_RD32(par->PMC, 0xabcd);
+ P = (pll >> 16) & 0x07;
+ pll = NV_RD32(par->PMC, 0xabcd);
+ M = pll & 0xFF;
+ N = (pll >> 8) & 0xFF;
+ if (((par->Chipset & 0xfff0) == 0xklmn) ||
+ ((par->Chipset & 0xfff0) == 0xklmn)) {
+ MB = 1;
+ NB = 1;
+ } else {
+ MB = (pll >> 16) & 0xFF;
+ NB = (pll >> 24) & 0xFF;
+ }
+ *MClk = ((N * NB * par->CrystalFreqKHz) / (M * MB)) >> P;
+
+ pll = NV_RD32(par->PMC, 0xZ000);
+ P = (pll >> 16) & 0x07;
+ pll = NV_RD32(par->PMC, 0xZ00Z);
+ M = pll & 0xFF;
+ N = (pll >> 8) & 0xFF;
+ MB = (pll >> 16) & 0xFF;
+ NB = (pll >> 24) & 0xFF;
+ *NVClk = ((N * NB * par->CrystalFreqKHz) / (M * MB)) >> P;
+ }
+ else if (par->Architecture >= NV_ARCH_40) {
pll = NV_RD32(par->PMC, 0x4020);
P = (pll >> 16) & 0x07;
pll = NV_RD32(par->PMC, 0x4024);
@@ -896,6 +923,11 @@
state->control = NV_RD32(par->PRAMDAC0, 0x0580) &
0xeffffeff;
/* fallthrough */
+ case NV_ARCH_50:
+ if (!par->FlatPanel)
+ state->control = NV_RD32(par->PRAMDAC0, 0xffff) &
+ 0xeffffeff;
+ /* fallthrough */
case NV_ARCH_10:
case NV_ARCH_20:
case NV_ARCH_30:
diff -u nvidia//nvidia.c /tmp/nvidia//nvidia.c
--- nvidia//nvidia.c 2010-03-15 19:09:39.000000000 +0300
+++ /tmp/nvidia//nvidia.c 2010-03-28 18:51:35.410412200 +0400
@@ -1194,6 +1194,9 @@
case NV_ARCH_40:
info->fix.accel = FB_ACCEL_NV_40;
break;
+ case NV_ARCH_50:
+ info->fix.accel = FB_ACCEL_NV_40;
+ break;
}
NVTRACE_LEAVE();
@@ -1266,6 +1269,10 @@
case 0x03D0:
arch = NV_ARCH_40;
break;
+ case 0x0197: /* Geforce 8880GTX */
+ case 0x05E7: /* Geforce285 */
+ arch = NV_ARCH_50;
+ break;
case 0x0020: /* TNT, TNT2 */
arch = NV_ARCH_04;
break;
diff -u nvidia//nv_type.h /tmp/nvidia//nv_type.h
--- nvidia//nv_type.h 2010-03-15 19:09:39.000000000 +0300
+++ /tmp/nvidia//nv_type.h 2010-03-28 18:47:04.343410440 +0400
@@ -12,6 +12,7 @@
#define NV_ARCH_20 0x20
#define NV_ARCH_30 0x30
#define NV_ARCH_40 0x40
+#define NV_ARCH_50 0x50
#define BITMASK(t,b) (((unsigned)(1U << (((t)-(b)+1)))-1) << (b))
#define MASKEXPAND(mask) BITMASK(1?mask,0?mask)
pavel@suse64:/usr/src/linux/drivers/video> diff -u nvidia/ /tmp/nvidia/ > /tmp/patch
pavel@suse64:/usr/src/linux/drivers/video> cat /tmp/patch
diff -u nvidia//nv_hw.c /tmp/nvidia//nv_hw.c
--- nvidia//nv_hw.c 2010-03-15 19:09:39.000000000 +0300
+++ /tmp/nvidia//nv_hw.c 2010-03-28 18:50:25.871159601 +0400
@@ -82,6 +82,8 @@
if (par->Architecture == NV_ARCH_40)
NV_WR32(par->PRAMDAC, 0x0300, NV_RD32(par->PRAMDAC, 0x0300));
+ if (par->Architecture == NV_ARCH_50)
+ NV_WR32(par->PRAMDAC, 0x0abc, NV_RD32(par->PRAMDAC, 0xabc));
return (cur & 0x01);
}
@@ -143,7 +145,32 @@
{
unsigned int pll, N, M, MB, NB, P;
- if (par->Architecture >= NV_ARCH_40) {
+ if (par->Architecture >= NV_ARCH_50) {
+ pll = NV_RD32(par->PMC, 0xabcd);
+ P = (pll >> 16) & 0x07;
+ pll = NV_RD32(par->PMC, 0xabcd);
+ M = pll & 0xFF;
+ N = (pll >> 8) & 0xFF;
+ if (((par->Chipset & 0xfff0) == 0xklmn) ||
+ ((par->Chipset & 0xfff0) == 0xklmn)) {
+ MB = 1;
+ NB = 1;
+ } else {
+ MB = (pll >> 16) & 0xFF;
+ NB = (pll >> 24) & 0xFF;
+ }
+ *MClk = ((N * NB * par->CrystalFreqKHz) / (M * MB)) >> P;
+
+ pll = NV_RD32(par->PMC, 0xZ000);
+ P = (pll >> 16) & 0x07;
+ pll = NV_RD32(par->PMC, 0xZ00Z);
+ M = pll & 0xFF;
+ N = (pll >> 8) & 0xFF;
+ MB = (pll >> 16) & 0xFF;
+ NB = (pll >> 24) & 0xFF;
+ *NVClk = ((N * NB * par->CrystalFreqKHz) / (M * MB)) >> P;
+ }
+ else if (par->Architecture >= NV_ARCH_40) {
pll = NV_RD32(par->PMC, 0x4020);
P = (pll >> 16) & 0x07;
pll = NV_RD32(par->PMC, 0x4024);
@@ -896,6 +923,11 @@
state->control = NV_RD32(par->PRAMDAC0, 0x0580) &
0xeffffeff;
/* fallthrough */
+ case NV_ARCH_50:
+ if (!par->FlatPanel)
+ state->control = NV_RD32(par->PRAMDAC0, 0xffff) &
+ 0xeffffeff;
+ /* fallthrough */
case NV_ARCH_10:
case NV_ARCH_20:
case NV_ARCH_30:
diff -u nvidia//nvidia.c /tmp/nvidia//nvidia.c
--- nvidia//nvidia.c 2010-03-15 19:09:39.000000000 +0300
+++ /tmp/nvidia//nvidia.c 2010-03-28 18:51:35.410412200 +0400
@@ -1194,6 +1194,9 @@
case NV_ARCH_40:
info->fix.accel = FB_ACCEL_NV_40;
break;
+ case NV_ARCH_50:
+ info->fix.accel = FB_ACCEL_NV_40;
+ break;
}
NVTRACE_LEAVE();
@@ -1266,6 +1269,10 @@
case 0x03D0:
arch = NV_ARCH_40;
break;
+ case 0x0197: /* Geforce 8880GTX */
+ case 0x05E7: /* Geforce285 */
+ arch = NV_ARCH_50;
+ break;
case 0x0020: /* TNT, TNT2 */
arch = NV_ARCH_04;
break;
diff -u nvidia//nv_type.h /tmp/nvidia//nv_type.h
--- nvidia//nv_type.h 2010-03-15 19:09:39.000000000 +0300
+++ /tmp/nvidia//nv_type.h 2010-03-28 18:47:04.343410440 +0400
@@ -12,6 +12,7 @@
#define NV_ARCH_20 0x20
#define NV_ARCH_30 0x30
#define NV_ARCH_40 0x40
+#define NV_ARCH_50 0x50
#define BITMASK(t,b) (((unsigned)(1U << (((t)-(b)+1)))-1) << (b))
#define MASKEXPAND(mask) BITMASK(1?mask,0?mask)
... ну и так далее
Кому фреймбуфер нужен? Мне иль Вам?
В общем, дорогу осилит идущий, а не ноющий. :)